1. Field of Invention
The present invention relates to a method of fabricating dynamic random access memory. More particularly, the present invention relates to an electrostatic discharge protection circuit structure of a dynamic random access memory and its method of manufacture.
2. Description of Related Art
Dynamic random access memory (DRAM) is a type of memory whose data are stored in an array of capacitors above a semiconductor substrate. The kind of data stored depends on the charging state of a capacitor. In general, a single bit of data is stored in a capacitor. A fully discharged capacitor represents a logic state of "0" while a fully charged capacitor represents a logic state of "1". If the electrodes of a capacitor in a DRAM are assembled correctly and the dielectric layer is uniformly built, the area of the electrode determines the amount of charges stored in a capacitor when the specified operating voltage is applied.
Read/write operation of a capacitor is achieved by selectively coupling the capacitor to a bit line so that electric charges can flow to the capacitor. Selective coupling of the capacitor is obtained through a transfer field effect transistor (transfer FET). Normally, the bit line is connected to one of the source/drain terminals of the transfer FET, and the other source/drain terminal of the transfer FET is connected to the capacitor. A word line is connected to the gate terminal of the transfer FET. By applying proper signal to the word line, flow of electric charges between the bit line and the capacitor can be controlled.
In general, in the fabrication of a capacitor over bit-line (COB) DRAM structure, an electrostatic discharge (ESD) protection circuit is also formed to protect the DRAM against any accidental damage due to external electrostatic discharge.
FIGS. 1A through 1G are cross-sectional views showing the progression of manufacturing steps in fabricating the electrostatic discharge protection circuit and capacitor of a DRAM according to a conventional method.
First, a semiconductor substrate 10 is provided as shown in FIG. 1A, and then an isolating structure 12 is formed over the substrate 10 defining a device region 14 and an ESD protective circuit region 16. The isolating structure 12 can be a shallow trench isolating structure or a field oxide layer, for example. Thereafter, a gate oxide layer 18, a polysilicon layer 20 and an oxide layer 22 are formed sequentially over the substrate structure.
Next, the oxide layer 22, the polysilicon layer 20 and the gate oxide layer 18 are patterned in sequence as shown in FIG. 1B. Ultimately, gate structures 24 and 26 are respectively formed in the device region 14 and the ESD protective circuit region 16. The gate structures 24 and 26 are both composite layers composed of a gate oxide layer 18a, a polysilicon layer 20a and an oxide layer 22a. In the subsequent step, an ion implant operation is carried out to implant ions into the semiconductor substrate 10 on the sides of the gate structures 24 and 26 to form lightly doped drain (LDD) source/drain regions 28 and 30.
Next, as shown in FIG. 1C, a layer of silicon nitride material having a thickness of about 1000 .ANG. is deposited over the substrate structure using, for example, a plasma-enhanced chemical vapor deposition (PECVD) method. Subsequently, the silicon nitride layer is etched back to form spacers 32 and 34 on the sidewalls of the gate structures 24 and 26 using, for example, an anisotropic etching method. Thereafter, a second ion implantation is carried out to implant ions into the substrate to form heavily doped source/drain regions 28a, 28b and 30a. Later, a dielectric layer 36 is formed covering the entire substrate structure using, for example, a low-pressure chemical vapor deposition (LPCVD) method. The dielectric layer 36 can be made from tetra-ethyl-ortho-silicate (TEOS), for example.
Next, as shown in FIG. 1D, the dielectric layer 36 is patterned by first forming a photoresist layer. Then, a contact opening 38 that expose the source/drain region 28b (for example, a source region) is formed in the device region 14 using, for example, a dry etching method. The contact opening 38 is subsequently used to form a bit line. Thereafter, the photoresist layer is removed, and a doped polysilicon layer 40 having a thickness of about 1000 .ANG. is formed over the substrate structure using, for example, a low-pressure chemical vapor deposition method. The doped polysilicon layer 40 also completely fills the contact opening 38 to make an electrical contact with the exposed source/drain region 28b.
Next, the polysilicon layer 40 is patterned to form a polysilicon layer 40a using conventional photolithographic and etching processes as shown in FIG. 1E. The polysilicon layer 40a serves as a bit line for the DRAM. Thereafter, a dielectric layer 42 having a thickness of about 7000 .ANG. is formed over the dielectric layer 36 and the polysilicon layer 40a using, for example, a plasma-enhanced chemical vapor deposition method. The dielectric layer 42 can be made from material including phosphosilicate glass (PSG). Subsequently, the dielectric layer 42 and the dielectric layer 36 in the device area 14 are sequentially etched to form contact openings 44 of the capacitor using, for example, a dry etching method. The contact openings expose the source/drain regions 28a. Then, a polysilicon layer 46 is formed over the entire substrate structure. The polysilicon layer 46 also fills the contact openings 44 so that the exposed source/drain regions 28a are electrically connected.
Next, as shown in FIG. 1F, conventional photolithographic and etching techniques are used to pattern the polysilicon layer 46 forming a polysilicon layer 46a. The polysilicon layer 46a functions as the lower electrode of a DRAM capacitor. Thereafter, a dielectric layer 48 and another polysilicon layer 50 are sequentially formed over the lower electrode. The dielectric layer 48, for example, can be an oxide/nitride/oxide (ONO) composite layer, and the polysilicon layer 50 functions as the upper electrode of the DRAM capacitor. Subsequently, a borophosphosilicate glass (BPSG) layer 52 is formed over the entire substrate structure using, for example, a plasma-enhanced chemical vapor deposition method. After that, the BPSG layer 52, the dielectric layer 42 and the dielectric layer 36 in the ESD protection circuit region 16 are sequentially patterned to form contact openings 54 and 56 using, for example, a dry etching method. The contact opening 54 exposes the gate structures 26, while the contact opening 56 exposes the source/drain regions 30a.
Next, as shown in FIG. 1G, conductive material such as tungsten is deposited over the substrate structure to form a conductive layer 58 using a chemical vapor deposition method, for example. The conductive layer 58 also fills the contact openings 54 and 56 so that the exposed gate structures 26 and the exposed source/drain regions 30a are electrically connected. Subsequently, the conductive layer 58 is patterned to form the DRAM's ESD protection circuit as shown in FIG. 1G.
Finally, subsequent operations necessary for forming the DRAM structure is performed. Since those manufacturing operations are familiar to semiconductor technologists and have no direct relation to this invention, detailed description is omitted here.
In the aforementioned method of production, the ESD protective circuit and the capacitors are completed at the same time without additional operations. However, the conventional DRAM's ESD protective circuit has a lightly doped drain (LDD) structure. Therefore, the degree of utilization of hot carrier in electrostatic discharge is low, and hence the extent of electrostatic discharge protection is poor. Consequently, DRAM may be insufficiently protected and damages caused by electrostatic discharge may be common.
In light of the foregoing, there is a need to provide an improved ESD protective circuit structure for DRAM together with the method of fabricating the structure.